/*
Copyright (c) 2019 Alibaba Group Holding Limited

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/
#include "stdio.h"
#include "vtimer.h"
#include "datatype.h"
#include "iopmp_cfg.h"
#include "my_timer.h"
#include "pmu.h"

//*******************************
//             PMU
//*******************************
#define PMU_BASE 0x60030000

#define PMU_EN_REG  0X00
#define PMU_PC_REG  0X04
//*******************************
//          IOPMP
//*******************************
#define IOPMP_BASE            0xF0400000
#define IOPMP_ID_REG          0X00
#define SIOPMP_RULE_REG       0X04
#define DIOPMP_BEGIN_CNT_REG  0X08
#define DIOPMP_DSIZE_CNT_REG  0X0C
#define DIOPMP_RULE_REG       0X10
#define DIOPMP_MODE_REG       0X14
#define SDIOPMP_ERROR_REG     0X18

#define DMA_BY_DEP  0xfff
#define DMA_REE_INC_START_PC 0xf0000000 //ree的程序在tee的iram中的地址
#define DMA_BY_DEST_BASE     0x20025000 //定义dest地址
#define DMA_BY_SRC_BASE      0x00008000//定义src地址
#define DMA_BLK_NUM          0X01      //DMA搬移block的数量

//*******************************
//          USI0 UART
//*******************************
#define USI0_BADDR  0x50028000
#define USI2_BADDR  0x50029000

#define USI1_BADDR  0x60028000
#define REG32(addr) *((volatile unsigned int *)(addr))

#define USI_CTRL    0x00
#define MODE_SEL    0x04
#define TX_FIFO     0x08
#define RX_FIFO     0x08
#define FIFO_STA    0x0c
#define CLK_DIV0    0x10
#define UART_CTRL   0x18
#define UART_STA    0x1c
//*******************************
//          SRAM
//*******************************
#define SRAM_BASE_ADDR 0x50024000
#define ONEKB_ADDR 0x400
//*******************************
//          TIMER
//*******************************

#define TIM0_BASE 0x50000000
#define TIM2_BASE 0x50000400

#define TIMER1_LD_CNT   0X00
#define TIMER1_CUR_VLU  0X04
#define TIMER1_CTRL_REG 0X08
#define TIMER1_INT_CLR  0X0C
#define TIMER1_INT_STA  0X10

#define TIMER2_LD_CNT   0X14
#define TIMER2_CUR_VLU  0X18
#define TIMER2_CTRL_REG 0X1C
#define TIMER2_INT_CLR  0X20
#define TIMER2_INT_STA  0X24

//*******************************
//          MAILBOX
//*******************************
#define REE2TEE_BASE 0x40010000

#define REE2TEE_REG0 0X00
#define REE2TEE_REG1 0X04
#define REE2TEE_REG2 0X08
#define REE2TEE_REG3 0X0C
#define REE2TEE_ACCESS_ERROR 0X10

#define TEE2REE_BASE 0x40020000

#define TEE2REE_REG0 0X00
#define TEE2REE_REG1 0X04
#define TEE2REE_REG2 0X08
#define TEE2REE_REG3 0X0C
#define TEE2REE_ACCESS_ERROR 0X10
typedef struct
{
  uint32_t  begin_cnt;
  uint32_t size_cnt;
  uint32_t rule;
  uint32_t mode;
}diopmp_config;



void iopmp_config_enable(char iopmpID,unsigned int en_disen)
{
  REG32(IOPMP_BASE + IOPMP_ID_REG) = ((en_disen<<5)&0x00000020) | (iopmpID&0x0000001F); //'b100001
}

void siopmp_rule_set(char Device,char rule)
{
   iopmp_config_enable(1,1);
   REG32(IOPMP_BASE + SIOPMP_RULE_REG) = (((unsigned int)rule) << (Device<<1)) | (~(0x3<<(Device<<1)));
   iopmp_config_enable(0,0);
}


void diopmp_rule_set(char Device,diopmp_config *diopmp_config )
{
   iopmp_config_enable(3,1);
  //  REG32(IOPMP_BASE + SIOPMP_RULE_REG) = (((unsigned int)rule) << (Device<<1)) | (~(0x3<<(Device<<1)));
  REG32(IOPMP_BASE + DIOPMP_BEGIN_CNT_REG) = diopmp_config->begin_cnt;
  REG32(IOPMP_BASE + DIOPMP_DSIZE_CNT_REG) = diopmp_config->size_cnt;
  REG32(IOPMP_BASE + DIOPMP_RULE_REG) = diopmp_config->rule;
  REG32(IOPMP_BASE + DIOPMP_MODE_REG) = diopmp_config->mode;
   iopmp_config_enable(0,0);
}


uint32_t siopmp_rule_read(void)
{
    uint32_t data=0;
   iopmp_config_enable(1,0);
   data = REG32(IOPMP_BASE + SIOPMP_RULE_REG);
   iopmp_config_enable(0,0);
   return data;
}

void diopmp_rule_read(void)
{
    uint32_t data=0;
   iopmp_config_enable(2,0);
   printf("diopmp begin count: 0x%x\n",REG32(IOPMP_BASE + DIOPMP_BEGIN_CNT_REG));
   printf("diopmp size count: 0x%x\n",REG32(IOPMP_BASE + DIOPMP_DSIZE_CNT_REG));
   printf("diopmp rule: 0x%x\n",REG32(IOPMP_BASE + DIOPMP_RULE_REG));
   printf("diopmp mode: 0x%x\n",REG32(IOPMP_BASE + DIOPMP_MODE_REG));
   
   iopmp_config_enable(0,0);
   return data;
}


int tee_main (void)
{
    static diopmp_config diopmp_reg_config;

    int int_dma_flag=0;
    int i =0;
    uint32_t data_check=0;
    uint32_t dma_index;
    uint32_t dma_jndex;
    PMU_InitTypeDef pmu_initstruct;

    printf("---------------------------------\n");
    printf("-------------TEE-----------------\n");
    printf("---------------------------------\n");
    printf("tee core process : running safety procedures\n");
    

    pmu_initstruct.pmu_set_iram_len = 0x00010000;
    pmu_initstruct.pmu_set_iram_addr = 0x90000000;
    pmu_initstruct.pmu_iram_dec_en = ENABLE;
    Init_Iram_Bus_Param(&pmu_initstruct);
    data_check = *(volatile uint32_t *) (0x0000004c);
    printf("tee core process : tee core data is %x\r\n",data_check);
    //在访问ree总线的iram时先复位ree pc指针
    *(volatile uint32_t *)(PMU_BASE+PMU_PC_REG) = 0x00000000;
    data_check = *(volatile uint32_t *) (0x9000004c);

    //设置REE的IOPMP访问权限，限制REE对USI0的访问
    printf("tee core process : SET IOPMP rule\r\n");
     //USI0 W
    
    siopmp_rule_set(USI0,READ_WRITE);
    
    // diopmp_reg_config.begin_cnt = 0x3;
    // diopmp_reg_config.size_cnt = 0x1;
    // diopmp_reg_config.rule =  0x3; // USI0 can't r/w CLK_DIV0
    // diopmp_reg_config.mode = 0x0; // reg,4bit,4bit
    // diopmp_rule_set(USI0,&diopmp_reg_config);
    diopmp_reg_config.begin_cnt = 0x0;
    diopmp_reg_config.size_cnt = 0x1;
    diopmp_reg_config.rule =  0x3; // USI0 can't r/w CLK_DIV0
    diopmp_reg_config.mode = 0x100; // reg,4bit,4bit
    diopmp_rule_set(SRAM,&diopmp_reg_config);
    
    REG32(USI0_BADDR+CLK_DIV0) = 0x11;
    REG32(USI0_BADDR+MODE_SEL) = 0x1;

    //检查设置的权限情况
    diopmp_rule_read();
    data_check = siopmp_rule_read();
    printf("tee core process : SIOPMP rule is %x\r\n",data_check);
    printf("tee core process : Source iopmp no limit\n");
    printf("tee core process : DIOPMP limit ree write data SRAM in range of 0~1kb \n");
    printf("========================================\n");  
    printf("=============TEE Write/Read  SRAM=======\n");  
    printf("========================================\n");  
    // //打印提示信息 ： 唤醒REE core
    printf("tee core process : write SRAM \n");
    for (uint16_t i = 0; i < 4; i++)
    {
      REG32(SRAM_BASE_ADDR+(i<<2)) = 0Xaabbcc00+i;
    }
      for (uint16_t i = 0; i < 4; i++)
    {
      REG32(SRAM_BASE_ADDR+ONEKB_ADDR+(i<<2)) = 0Xaabbcc00+i;
    }
    printf("tee core process : read SRAM \n");
        for (uint16_t i = 0; i < 4; i++)
    {
      printf("tee core process: sram 0x%x data :0x%x \n",(SRAM_BASE_ADDR+(i<<2)),REG32(SRAM_BASE_ADDR+(i<<2)));
    }
      for (uint16_t i = 0; i < 4; i++)
    {
      printf("tee core process: sram 0x%x data 1K :0x%x \n",(SRAM_BASE_ADDR+ONEKB_ADDR+(i<<2)),REG32(SRAM_BASE_ADDR+ONEKB_ADDR+(i<<2)));
    }
        printf("tee core process : tee core wakes up ree core\n");
     Weak_Up_Ree_Core(0x90000000);
     while (1)
     {
      /* code */;
     }
     
  //     while(1)
	//  {
    
  //              tee_timer_delay(2000);
  //               if(i == 10){
  //                        diopmp_reg_config.begin_cnt = 0x3;
  //                        diopmp_reg_config.size_cnt = 0x1;
  //                        diopmp_reg_config.rule =  0x7; // USI0 can't w CLK_DIV0
  //                        diopmp_reg_config.mode = 0x0; // reg,4bit,4bit
  //                        diopmp_rule_set(USI0,&diopmp_reg_config);
                               
  //                         REG32(USI0_BADDR+CLK_DIV0) = 0x11;
  //                         printf("tee : USI0 can't w CLK_DIV0\n"); 
  //                        //diopmp_rule_read();
  //                     }
  //               else if(i == 20)
  //                    {
  //                        diopmp_reg_config.begin_cnt = 0x3;
  //                        diopmp_reg_config.size_cnt = 0x1;
  //                        diopmp_reg_config.rule =  0xf; // USI0 w r CLK_DIV0
  //                        diopmp_reg_config.mode = 0x0; // reg,4bit,4bit
                         
  //                        diopmp_rule_set(USI0,&diopmp_reg_config);
  //                        printf("tee : USI0 wr CLK_DIV0\n");
  //                        //diopmp_rule_read();

                            
  //                     }
  //                 else if(i == 30)
  //                    {
	// 			                 diopmp_reg_config.begin_cnt = 0x13;                         
	// 			                 diopmp_reg_config.size_cnt = 0x11;
  //                        diopmp_reg_config.rule =  0x7B; // USI0 w r CLK_DIV0
  //                        diopmp_reg_config.mode = 0x0; // reg,4bit,4bit
                         
  //                        diopmp_rule_set(USI0,&diopmp_reg_config);
  //                        REG32(USI0_BADDR+MODE_SEL) = 0x1;
  //                        printf("tee : USI0  CLK_DIV0 w CTRL r\n");  
  //                               i = 0;
  //                    }
                     
  //                i++;
	//  }

  //     while(1)
	//  {
  //              tee_timer_delay(1000);
  //               if(i == 10){
  //                    siopmp_rule_set(USI0,READ);
  //                    REG32(USI0_BADDR+CLK_DIV0) = 0x11;
  //                                data_check = iopmp_rule_read();
  //                   printf("tee core process : IOPMP rule is %x\r\n",data_check);
  //                    printf("tee core process : change USI0 read only\r\n");
  //                     }
  //               else if(i == 20)
  //                    {
  //                           siopmp_rule_set(USI0,READ_WRITE);
  //                                data_check = iopmp_rule_read();
  //                         printf("tee core process : IOPMP rule is %x\r\n",data_check);
  //                           printf("tee core process : change USI0 read write\r\n");
  //                           i = 0;
  //                     }
  //                   else;
                     
  //                i++;
	//  }
            sim_end(); 

}

int ree_main (void)
{
    printf("\n");
    printf("---------------------------------\n");
    printf("------REE Write/Read  SRAM-------\n");
    printf("---------------------------------\n");

    // while(1)
    // {
    //     //   printf("REE core process : USI2 0x%x \r\n",REG32(USI2_BADDR+CLK_DIV0));
    //       //printf("REE core process : USI0 0x%x \r\n",REG32(USI0_BADDR+CLK_DIV0));
    //       printf("REE : USI0 USI_CTRL 0x%x \r\n",REG32(USI0_BADDR+MODE_SEL));
    //       printf("REE : USI0 CLK_DIV0 0x%x \r\n",REG32(USI0_BADDR+CLK_DIV0));
    //       REG32(USI0_BADDR+MODE_SEL) = 0x2;
    //       REG32(USI0_BADDR+CLK_DIV0) = 0x67;



    //        ree_timer_delay (0x1000);
    //          // verify whether REE can mod IOPMP reg
    //     //*(volatile uint32_t *)(IOPMP_BASE+IOPMP_RULE_REG) = 0xFFFFFFFF; 
    //      //ree_timer_delay (2000);
    //      //sim_end(); 


             
    // };
    printf("ree core process : write SRAM \n");
    for (uint16_t i = 0; i < 4; i++)
    {
      REG32(SRAM_BASE_ADDR+(i<<2)) = 0Xffee1200+i;
    }
      for (uint16_t i = 0; i < 4; i++)
    {
      REG32(SRAM_BASE_ADDR+ONEKB_ADDR+(i<<2)) = 0Xffee1200+i;
    }
    printf("ree core process : read SRAM \n");
        for (uint16_t i = 0; i < 4; i++)
    {
      printf("ree core process: sram 0x%x data :0x%x \n",(SRAM_BASE_ADDR+(i<<2)),REG32(SRAM_BASE_ADDR+(i<<2)));
    }
      for (uint16_t i = 0; i < 4; i++)
    {
      printf("ree core process: sram 0x%x data 1K :0x%x \n",(SRAM_BASE_ADDR+ONEKB_ADDR+(i<<2)),REG32(SRAM_BASE_ADDR+ONEKB_ADDR+(i<<2)));
    }
   
    sim_end(); 

    
}



    // for (dma_jndex = 0;dma_jndex < 8; dma_jndex++)
    // {
    //     for (dma_index = 0;dma_index < DMA_BY_DEP/4+1; dma_index++)
    //     {
    //         data_check = *(volatile uint32_t *) (DMA_BY_SRC_BASE + dma_jndex * (DMA_BY_DEP + 0x1) + dma_index * 4);
    //         printf("%x\r\n",data_check);
    //     }
    //     printf("ree core process : this is %d block!\n",dma_jndex);
    // }


